64b/66b encoding

In data networking and transmission, 64b/66b is a line code that transforms 64-bit data to 66-bit line code to provide enough state changes to allow reasonable clock recovery and facilitate alignment of the data stream at the receiver.

The overhead of the 64b/66b encoding is considerably less than the more common 8b/10b encoding scheme.

Function

As the scheme name suggests, 64 bits of data are transmitted as a 66-bit entity.

The 66 bit entity is made by prefixing one of two possible two-bit 'preambles' to the 64 bits to be transmitted.

• If the preamble is '01', the 64 bits are entirely data
• If the preamble is '10', an eight-bit type field follows, plus 56 bits of control information and/or data
• The preambles '00' and '11' are not used, and generate an error if seen.

The use of the '01' and '10' preambles guarantees a bit transition every 66 bits, which means that a continuous stream of 0s or 1s cannot be valid data. It also allows easier clock/timer synchronization, as a transition must be seen every 66 bits.

The 56 or 64 bits of data are then scrambled using a self-synchronous scrambler function, with the intention of ensuring that a relatively even distribution of 1s and 0s are normally found in the transmitted data. The intention is not to encrypt the data, but to give the transmitted data useful engineering properties. This does not guarantee that pathological data will not generate a transmitted output that has all 0s or all 1s or other undesirable properties, but simply reduces the probability that this will occur with normal data. This method is different from the codebook based approach of 8B/10B encoding.

The encoding and scrambling are normally done entirely in hardware, the scrambling using a linear feedback shift register. Upper layers of the software stack need not be aware that the link layer is using this code.

Properties and application

64b/66b's design goals are clock recovery and stream realignment, but not DC balance or run length limitation. If the scrambling pattern and the data happen to be aligned, continuous runs of 65 zeros and 65 ones (maximum strain for clock recovery) can occur as well as continuous runs of 1 one and 65 zeros or 1 zero and 65 ones (maximum DC imbalance). This makes the encoding scheme suitable and efficient for optical transmissions, but problematic for electrical signaling.

The Interlaken protocol addresses this by using the 64b/67b encoding. 64b/67b extends 64b/66b with DC balancing, making it suitable for use on electrical media.

Technologies that use it

• Fibre Channel 10GFC
• 10 Gigabit Ethernet
• 10G-EPON, 10 Gbit/s Ethernet Passive Optical Network
• Aurora, from Xilinx
• InfiniBand

External links

• 64b/66b low-overhead coding proposal for serial links (update 1/12/00)

Note that this is the original proposal to the IEEE, and some changes were made for the final, agreed standard e.g. the scrambling polynomial is neither of the two options outlined in the paper, but actually x⁵⁸+x³⁹+1

• PatentView/EP1133123 Software Patent: 64b/66b decoding, for packetized serial data
• ERROR CORRECTION ON 64/66 BIT ENCODED LINKS
• Introduction to 10 Gigabit 64b/66b (Clause 49)
• A reference design by Xilinx on 64b/66b encoding and scrambling
• Aurora 64B66B IP core using 64b/66b encoding